The present invention relates generally to flat chip carrier packages utilized for accommodating the interconnection of a plurality of electrical leads accompanying electronic active components, and in particular to a stackable flat chip carrier package which can be utilized by leadless, as well as integrated circuit devices with leads, wherein the associated electrical interconnections are accomplished without solder, enabling high volumetric efficiency to be realized by the vertical stacking of the individual integrated circuit chips within the unique design of this stackable chip carrier package.
One of the important trends in the electronics industry has been the utilization of integrated circuits as individual components due to their relatively inexpensive cost, miniaturized size, and electrical dependability. Today it is common for hundreds of complex integrated circuits to be treated as discrete components by the design engineer, with such integrated circuits being appropriately packaged and electrically connected to their associated printed circuit boards.
The challenge to the product design engineer has been to increase the number of integrated circuits utilized within the limited space requirements of the associated printed circuit board. Because of the density of the total number of electrical components required by increasingly complex designs created by the development engineer, the available space confronting the design engineer is constantly optimized during the design phase of those skilled in the art. This has led to the creative packaging of integrated circuits in such a manner as to yield greater component density for a given amount of printed circuit board space.
It has long been the case that standard approaches have resulted in the vertically stacking of electronic packages, each containing a single integrated circuit, in some manner, to obtain greater volummetric efficiency: this has resulted in more complex interconnections and a corresponding increase in the size of the package to adequately protect and facilitate such electrical interconnections. The interconnections have to be made in such a manner to be reliable, economical, and allow the removal and replacement of a defective integrated circuit from a printed circuit board without the necessity for labor-intensive, time-consuming, soldering techniques. Furthermore, as the vertical stacking of such electronic packages have occurred, due to the close proximity of adjacent electrical circuit boards within the electronic package, it became critical to have an appropriate means to regulate the height of such stacking means, and have air circulate in the spaces between the fully operational printed circuit boards housed within the electronic product.
As the density of electrical components on a printed circuit board increases, it becomes increasingly important to maintain electrical isolation properties in the planer and vertical axis of the functional printed circuit board. The tradeoff has been to accomplish the required isolation properties, given the optimum size and available space parameters.
A common disadvantage relating to all of the foregoing known prior art devices involve the relatively high cost, and general complexity in the different quantities of unique piece-parts required, to comprise the various chip carrier packages.
Hence it has become desirable to design an improved chip carrier package, which allows facilitation of any electrical art work, has an inherent adaptable design allowing the single or multiple stack utilization of the same electrical connection, has fewer internal interconnecting parts, the use of a smaller diameter wire for bonding the integrated circuit to the chip carrier package proper, easy disassembly and removal of the integrated circuit chip for replacement or repair purposes, and the ability to accomplish what has been outlined at a lower cost than what is presently available in the prior art. The improved chip carrier package must also be sufficiently strong to withstand environmental vibrations during operation of the electronic apparatus.